AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 127
AT91RM9200-QU-002
Manufacturer Part Number
AT91RM9200-QU-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-QU-002.pdf
(701 pages)
3.AT91RM9200-QU-002.pdf
(38 pages)
Specifications of AT91RM9200-QU-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Processor Series
AT91Rx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, UART, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
122
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
122
Interface
EBI/EMI, UART/USART
Ios
122
Memory Type
ROM
Number Of Bits
32
Package Type
208-pin PQFP
Programmable Memory
128K Bytes
Timers
3-16-bit
Voltage, Range
1.65-1.95 V
Cpu Family
91R
Device Core
ARM920T
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
16KB
# I/os (max)
122
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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16.3.5
16.3.6
1768I–ATARM–09-Jul-09
Misalignment Detector
Memory Controller Interrupt
The Memory Controller features a Misalignment Detector that checks the consistency of the
accesses.
For each access, regardless of the master, the size of access and the 0 and 1 bits of the
address bus are checked. If the type of access is a word (32-bit) and the 0 and 1 bits are not 0,
or if the type of the access is a half-word (16-bit) and the 0 bit is not 0, an abort is returned to the
master and the access is cancelled. Note that the accesses of the ARM processor when it is
fetching instructions are not checked.
The misalignments are generally due to software errors leading to wrong pointer handling.
These errors are particularly difficult to detect in the debug phase.
As the requested address is saved in the Abort Status and the address of the instruction gener-
ating the misalignment is saved in the Abort Link Register of the processor, detection and
correction of this kind of software error is simplified.
The Memory Controller itself does not generate any interrupt. However, as indicated in
16-1, the Memory Controller receives an interrupt signal from the External Bus Interface, which
might be activated in case of Refresh Error detected by the SDRAM Controller. This interrupt
signal just transits through the Memory Controller, which can neither enable/disable it nor return
its activity.
This Memory Controller interrupt signal is ORed with the other System Peripheral interrupt lines
(RTC, ST, DBGU, PMC) to provide the System Interrupt on Source 1 of the Advanced Interrupt
Controller.
AT91RM9200
Figure
127
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