AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 655

IC ARM9 MCU 208 PQFP

AT91RM9200-QU-002

Manufacturer Part Number
AT91RM9200-QU-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91RM9200-QU-002

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Processor Series
AT91Rx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, UART, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
122
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
122
Interface
EBI/EMI, UART/USART
Ios
122
Memory Type
ROM
Number Of Bits
32
Package Type
208-pin PQFP
Programmable Memory
128K Bytes
Timers
3-16-bit
Voltage, Range
1.65-1.95 V
Cpu Family
91R
Device Core
ARM920T
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
16KB
# I/os (max)
122
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Table 38-8.
Notes:
1768I–ATARM–09-Jul-09
Symbol
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
BFC
1
2
3
4
5
6
7
9
10
15
16
21
22
23
24
25
26
1. The derating factor is not to be applied to t
2. a = Number of Address Valid Latency Cycles defined in the BFC_MR AVL field.
3. o = Number of Output Enable Latency Cycles defined in the BFC_MR OEL field.
4. Applicable only with multiplexed Address and Data Buses.
BFC Signals in Burst Mode
Parameter
BFCK Rising to A1-A25 Valid
BFCK Rising to A1-A25 Change
BFCK Falling to BFAVD Active
BFCK Falling to BFAVD Inactive
BFAVD Minimum Pulse Width
BFCK Rising to BFOE Active
BFCK Rising to BFOE Inactive
D0-D15 in Setup before BFCK Rising Edge
D0-D15 in Hold after BFCK Rising Edge
BFCK Rising to AD0-AD15 Valid
BFCK Rising to AD0-AD15 Not Valid
Number of Address Valid Latency Cycles
Number of Output Enable Latency Cycles
BFCK Falling to BFBAA Active
BFCK Falling to BFBAA Inactive
BFRDY Change Hold after BFCK Rising Edge
BFRDY Change Setup before BFCK Rising Edge
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1) (4)
(1)
CPBFCK
(4)
(1)
(1)
.
Conditions
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
ADD
ADD
ADD
ADD
BFAVD
BFAVD
BFAVD
BFAVD
BFAVD
BFAVD
BFOE
BFOE
BFOE
BFOE
DATA
DATA
DATA
DATA
BFBAA
BFBAA
BFBAA
BFBAA
= 0 pF
derating
= 0 pF
derating
derating
= 0 pF
derating
= 0 pF
= 0 pF
derating
= 0 pF
derating
= 0 pF
derating
= 0 pF
derating
= 0 pF
derating
derating
= 0 pF
derating
= 0 pF
t
t
t
t
t
(o
t
t
CPBFCK
CLBFCK
CLBFCK
CLBFCK
CLBFCK
t
CLBFCK
CLBFCK
((a + 1)
CPBFCK
x
0.028
0.028
0.028
0.001
0.028
0.028
0.028
0.028
0.028
- 0.4
- 1.1
- 0.1
Min
t
1.0
0.1
0.3
CPBFCK
(3)
- 1.0
- 1.1
- 1.8
+ 1.0
- 0.8
- 1.0
- 1.7
)
(2)
x
)
t
t
t
t
t
(o
t
CLBFCK
CLBFCK
CLBFCK
CLBFCK
CLBFCK
t
CLBFCK
CPBFCK
AT91RM9200
((a + 1)
x
0.045
0.044
0.044
0.044
0.044
0.044
0.044
0.044
Max
t
0.1
0.7
CPBFCK
(3)
+ 0.2
+ 0.1
- 0.2
- 0.3
- 0.2
- 0.1
)
(2)
x
)
Units
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
655

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