MC908AP32CFAE Freescale Semiconductor, MC908AP32CFAE Datasheet - Page 277

• Manufacturer Part Number: MC908AP32CFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 32
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

IMASK1 — IRQ1 Interrupt Mask Bit
MODE1 — IRQ1 Edge/Level Select Bit
17.6.2 IRQ2 Status and Control Register
The IRQ2 status and control register (INTSCR2) controls and monitors operation of IRQ2. The INTSCR2
has the following functions:
PUC0ENB — IRQ2 Pin Pullup Enable Bit.
IRQ2F — IRQ2 Flag Bit
ACK2 — IRQ2 Interrupt Request Acknowledge Bit
IMASK2 — IRQ2 Interrupt Mask Bit
MODE2 — IRQ2 Edge/Level Select Bit
Freescale Semiconductor
Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1.
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Setting this bit to logic 1 disables the pullup on PTC0/IRQ2 pin.
Reset clears this bit.
This read-only status bit is high when the IRQ2 interrupt is pending.
Writing a logic 1 to this write-only bit clears the IRQ2 latch. ACK2 always reads as logic 0. Reset clears
ACK2.
Writing a logic 1 to this read/write bit disables IRQ2 interrupt requests. Reset clears IMASK2.
This read/write bit controls the triggering sensitivity of the IRQ2 pin. Reset clears MODE2.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
1 = IRQ2 pin internal pullup is disabled
0 = IRQ2 pin internal pullup is enabled
1 = IRQ2 interrupt pending
0 = IRQ2 interrupt not pending
1 = IRQ2 interrupt requests disabled
0 = IRQ2 interrupt requests enabled
1 = IRQ2 interrupt requests on falling edges and low levels
0 = IRQ2 interrupt requests on falling edges only
Enables/disables the internal pullup device on IRQ2 pin
Shows the state of the IRQ2 flag
Clears the IRQ2 latch
Masks IRQ2 interrupt request
Controls triggering sensitivity of the IRQ2 interrupt pin
Address:
Reset:
Read:
Write:
Figure 17-5. IRQ2 Status and Control Register (INTSCR2)
$001C
Bit 7
0
0
PUC0ENB
= Unimplemented
6
0
MC68HC908AP Family Data Sheet, Rev. 4
5
0
0
4
0
0
IRQ2F
3
0
ACK2
2
0
0
IMASK2
1
0
MODE2
Bit 0
0
IRQ Registers
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