MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 173

• Manufacturer Part Number: MC9S12HZ128CAL
• Description: IC MCU 16BIT 128K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128CAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.2.2
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Read: anytime
Write: anytime except when PLLSEL = 1
5.3.2.3
This register is reserved for factory testing of the CRG module and is not available in normal modes.
Read: always reads 0x0000 in normal modes
Write: unimplemented in normal modes
Freescale Semiconductor
Reset
Reset
W
W
R
R
CRG Reference Divider Register (REFDV)
Reserved Register (CTFLG)
0
0
0
0
7
7
Write to this register initializes the lock detector bit and the track detector
bit.
Writing to this register when in special mode can alter the CRG
functionality.
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 5-5. CRG Reference Divider Register (REFDV)
Figure 5-6. CRG Reserved Register (CTFLG)
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
0
0
5
5
NOTE
NOTE
0
0
0
0
4
4
REFDV3
0
0
0
3
3
Chapter 5 Clocks and Reset Generator (CRGV4)
REFDV2
0
0
0
2
2
REFDV1
0
0
0
1
1
REFDV0
0
0
0
0
0
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