MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 38
![IC MCU 16BIT 128K FLASH 112-LQFP](/photos/12/21/122139/mc9s12hz128cal_sml.jpg)
MC9S12HZ128CAL
Manufacturer Part Number
MC9S12HZ128CAL
Description
IC MCU 16BIT 128K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12HZ128CAL.pdf
(692 pages)
Specifications of MC9S12HZ128CAL
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12HZ128CAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 1 MC9S12HZ256 Device Overview
1.5.3
This pin is reserved for test.
1.5.4
Dedicated pin used to create the PLL loop filter. Please ask your Freescale representative for the
interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be
avoided.
1.5.5
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
1.5.6
1.5.6.1
PAD7–PAD0 are general-purpose input or output pins and analog inputs for the analog-to-digital
converter. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.5.6.2
PA7–PA0 are general-purpose input or output pins. They can be configured as frontplane segment driver
outputs FP15–FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
38
TEST — Test Pin
XFC — PLL Loop Filter Pin
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode
Pin
Port Pins
PAD[7:0] / AN[7:0] / KWAD[7:0] — Port AD I/O Pins [7:0]
PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
The TEST pin must be tied to V
Figure 1-9. PLL Loop Filter Connections
MC9S12HZ256 Data Sheet, Rev. 2.05
MCU
XFC
SS
NOTE
in all applications.
V
DDPLL
R
C
S
V
DDPLL
C
P
Freescale Semiconductor
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