MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 587

• Manufacturer Part Number: MC9S12HZ128CAL
• Description: IC MCU 16BIT 128K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128CAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.8
Read: Anytime (provided this register is in the map).
Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following
pages.
Port E serves as general-purpose I/O or as system and bus control signals. The PEAR register is used to
choose between the general-purpose I/O function and the alternate control functions. When an alternate
control function is selected, the associated DDRE bits are overridden.
The reset condition of this register depends on the mode of operation because bus control signals are
needed immediately after reset in some modes. In normal single-chip mode, no external bus control signals
are needed so all of port E is configured for general-purpose I/O. In normal expanded modes, only the E
clock is configured for its alternate bus control function and the other bits of port E are configured for
general-purpose I/O. As the reset vector is located in external memory, the E clock is required for this
access. R/W is only needed by the system when there are external writable resources. If the normal
expanded system needs any other bus control signals, PEAR would need to be written before any access
that needed the additional signals. In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB, and
R/W are configured out of reset as bus control signals.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
Freescale Semiconductor
Normal Expanded Wide
Emulation Expanded
Emulation Expanded
Special Single Chip
Normal Single Chip
Normal Expanded
Special Test
Peripheral
Port E Assignment Register (PEAR)
Narrow
Narrow
Reset
Wide
W
R
NOACCE
0
0
0
1
1
0
0
0
7
Figure 21-12. Port E Assignment Register (PEAR)
= Unimplemented or Reserved
0
0
0
0
0
0
0
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05
6
PIPOE
0
1
0
1
1
0
0
0
5
NECLK
4
0
0
0
0
0
1
0
0
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
LSTRE
0
1
0
1
1
0
0
0
3
RDWE
0
1
0
1
1
0
0
0
2
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
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