MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 201
![IC MCU 16BIT 128K FLASH 112-LQFP](/photos/12/21/122139/mc9s12hz128cal_sml.jpg)
MC9S12HZ128CAL
Manufacturer Part Number
MC9S12HZ128CAL
Description
IC MCU 16BIT 128K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12HZ128CAL.pdf
(692 pages)
Specifications of MC9S12HZ128CAL
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12H
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
6 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
85
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12HZ128CAL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out
period. A premature write the CRG will immediately generate a reset.
As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock
monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching
the COP vector.
5.5.3
The on-chip voltage regulator detects when V
power-on reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered
the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates
a valid oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows
the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock
mode.
Figure 5-26
and when the RESET pin is held low.
Freescale Semiconductor
Power-On Reset, Low Voltage Reset
and
Figure 5-27
Internal RESET
RESET
Internal POR
Internal RESET
RESET
Internal POR
Figure 5-26. RESET Pin Tied to V
show the power-up sequence for cases when the RESET pin is tied to V
Figure 5-27. RESET Pin Held Low Externally
MC9S12HZ256 Data Sheet, Rev. 2.05
DD
Clock Quality Check
(no Self-Clock Mode)
Clock Quality Check
(no Self-Clock Mode)
128 SYSCLK
) (
to the MCU has reached a certain level and asserts
) (
128 SYSCLK
) (
) (
) (
) (
64 SYSCLK
DD
64 SYSCLK
(by a Pull-Up Resistor)
Chapter 5 Clocks and Reset Generator (CRGV4)
DD
201
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