M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 369

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 22.18 C0GMR1, C0LMAR1 and C0LMBR1 Registers and
2
0
1
9
C
3 .
B
8 /
0
1
3
0
3
J
G
4
CAN0 Global Mask Register Standard ID1
CAN0 Local Mask Register A Standard ID1
CAN0 Local Mask Register B Standard ID1
a
CAN0 Global Mask Register Extended ID0
CAN0 Local Mask Register A Extended ID0
CAN0 Local Mask Register B Extended ID0
b7
b7
0 -
n
o r
3 .
NOTES:
1
b6
NOTES:
u
b6
, 1
3
p
1
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
3. The C0LMAR1 register shares the same address with the C0MCTL1 register.
4. The C0LMBR1 register shares the same address with the C0MCTL9 register.
1. This register can be accessed when the BANKSEL bit in the C0CTLR1 register is set to "1".
2. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
3. The C0LMAR2 register shares the same address with the C0MCTL2 register.
4. The C0LMBR2 register shares the same address with the C0MCTL10 register.
b5
2
b5
(
C0GMR2, C0LMAR2 and C0LMBR2 Registers
M
0
supplying a clock to the CAN module after reset.
supplying a clock to the CAN module after reset.
0
b4
3
b4
6
2
C
b3
b3
Page 344
8 /
b2
b2
, 3
b1
M
b1
3
b0
b0
2
C
f o
8 /
(b7 - b6)
EID14M
EID15M
EID16M
EID17M
Symbol
SID0M
SID1M
SID2M
SID3M
SID4M
SID5M
Symbol
(b7 - 4)
4
3
Bit
8
Bit
) T
Symbol
C0GMR1
C0LMAR1
C0LMBR1
8
Symbol
C0GMR2
C0LMAR2
C0LMBR2
Standard ID0
Standard ID1
Standard ID2
Standard ID3
Standard ID4
Standard ID5
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Extended ID14
Extended ID15
Extended ID16
Extended ID17
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Bit Name
Address
022A
0232
023A
Address
0229
0231
0239
16 (3)
16
16 (4)
16
16
16
(3)
(4)
(1)
0: No ID is checked
1: ID is checked
0: No ID is checked
1: ID is checked
(1)
(1)
(1)
(1)
(1)
After Reset
XX00 0000
XX00 0000
XX00 0000
After Reset
XXXX 0000
XXXX 0000
XXXX 0000
Function
Function
2
2
2
(2)
(2)
2
2
2
RW
RW
RW
RW
RW
RW
RW
22. CAN Module
RW
RW
RW
RW
RW