M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 503

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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• Wrong values are stored in the ADij register (i=0,1; j=0 to 7) if the CPU reads the ADij register while the
• Conversion results of the A/Di is indeterminate if the ADST bit in the ADiCON0 register (i=0,1) is set to
0
ADij register is storing results from a completed A/D conversion. This occurs when the CPU clock is set
to a divided main clock or a sub clock.
In one-shot mode or single sweep mode, read the corresponding ADij register after verifying that the A/
D conversion has been completed. The IR bit in the ADiIC register can determine the completion of the
A/D conversion.
In repeat mode, repeat sweep mode 0 and repeat sweep mode 1, use an undivided main clock as the
CPU clock.
"0" (A/D conversion stopped) and the conversion is forcibly terminated by program. The ADij register
(j=0 to 7) not performing an A/D conversion may also be indeterminate.
If A/Di is forcibly terminated, do not use any values obtained from the ADij registers.
If either A/D0 or A/D1 is forcibly terminated while the ADS bit in the ADiCON2 register is set to "0"
(channel replacement disabled), the other A/D converter, A/Di, will perform normally. The values of ADij
registers not performing an A/D conversion remain unchanged.
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27. Precautions (A/D Converter)