M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 498

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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27.8.3 Timer B
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27.8.3.1 Timer B (Timer Mode, Event Counter Mode)
27.8.3.2 Timer B (Pulse Period/Pulse Width Measurement Mode)
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(a) TBiS (i=0 to 5) bit is set to "0" (stops counting) after reset. Set TBiS bit to "1" (starts counting) after
(b) The TBi register indicates the counter value during counting at any given time. However, the
(a) The IR bit in the TBiIC register is set to "1" (overflow) when the valid edge of a pulse to be mea-
(b) Count overflow on a different timer if an interrupt source cannot be determined by the MR3 bit,
(c) To set the MR3 bit in the TBiMR register to "0" (no overflow), set when the TBiS bit is set to "1"
(d) The IR bit in the TBiIC register is used to detect overflow only. Use the MR3 bit only to determine
(e) Indeterminate values are transferred to the reload register during the first valid edge input following
(f) The counter value is indeterminate at the start of a count. Therefore, the MR3 bit may change to "1"
(g) The IR bit may be set to "1" (interrupt requested) if the MR1 to MR0 bits in the TBiMR register are
(h) Pulse width measurement measures pulse width continuously. Use program to determine whether
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selecting an operation mode and setting the TBi register.
to 7 in the TBSR register.
counter will read "FFFF
register while the counter stops and before the counter starts counting.
sured is input and when the timer Bi counter overflows. The MR3 bit in the TBiMR register deter-
mines the interrupt source within an interrupt service routine.
such as when a pulse to be measured is input at the same time the timer overflows.
(count starts) and at least one count is counted after the MR3 bit is set to "1" (overflow).
interrupt source within an interrupt service routine.
the start of the count. Timer B interrupt request is not acknowledged at this time.
(overflow) and cause timer B interrupt requests to be generated, until a valid edge is input after the
count begins.
set to a different value after a count begins. If the MR1 to MR0 bits are rewritten, but to the same
value as before, the IR bit remains unchanged.
measurement results are high ('"H") or low ("L").
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The TB0S to TB2S bits are the bits 5 to 7 in the TABSR register. The TB3S to TB5S bits are bits 5
3 .
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" when reloading . The setting value can be read after setting the TBi
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27. Precautions (Timer)