HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 248
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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10.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 10.30 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
Table 10.30 Cascaded Combinations
Example of Cascaded Operation Setting Procedure: Figure 10.18 shows an example of the
setting procedure for cascaded operation.
Rev. 2.00, 09/04, page 206 of 720
Combination
Channels 1 and 2
and the counters operates independently in phase counting mode.
Cascaded Operation
<Cascaded operation>
Cascaded operation
Set cascading
Start count
Figure 10.18 Cascaded Operation Setting Procedure
Upper 16 Bits
TCNT_1
[1]
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
[2] Set the CST bit in TSTR for the upper and
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
lower channel to 1 to start the count
operation.
Lower 16 Bits
TCNT_2
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