HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 382

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.8
The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer.
With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the
communication mode. With a 7-bit data length, LSB-first transfer must be selected. The
description in this section assumes LSB-first transfer.
12.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 12.2 shows
the relationships between the N setting in BRR and the effective bit rate B
clocked synchronous modes. The initial value of BRR is H'FF, and it can be read or written to by
the CPU at all times.
Rev. 2.00, 09/04, page 340 of 720
Bit
7 to 4
3
2
1
0
Bit Name




DIR
Serial Direction Control Register (SDCR)
Bit Rate Register (BRR)
Initial
Value
All 1
0
0
1
0
R/W
R
R/W
R
R
R
Description
Reserved
The write value must always be 1. Operation cannot
be guaranteed if 0 is written.
Data Transfer Direction
Selects the serial/parallel conversion format. Valid for
an 8-bit transmit/receive format.
0: TDR contents are transmitted in LSB-first order
1: TDR contents are transmitted in MSB-first order
Reserved
The write value must always be 0. Operation cannot
be guaranteed if 1 is written.
Reserved
This bit is always read as 1, and cannot be modified.
Reserved
The write value must always be 0. Operation cannot
be guaranteed if 1 is written.
Receive data is stored in RDR in LSB-first
Receive data is stored in RDR in MSB-first
0
for asynchronous and