HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 583

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.3
Port D is an input/output port with the nine pins shown in figure 18.3.
18.3.1
Port D has the following register. For details on register addresses and register states during each
processing, refer to appendix A, Internal I/O Register.
• Port D data register L (PDDRL)
18.3.2
The port D data register L (PDDRL) is a 16-bit readable/writable register that stores port D data.
Bits PD8DR to PD0DR correspond to pins PD8 to PD0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PDDRL, that value is output
directly from the pin, and if PDDRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions is a general input, if PDDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PDDRL, although that value is written into PDDRL, it
does not affect the pin state. Table 18.3 summarizes port D data register L read/write operations.
Note: * Only for the F-ZTAT version (no corresponding function in the mask version.)
Port D
Port D
Register Descriptions
Port D Data Register L (PDDRL)
PD8 (I/O) / UBCTRG (output)*
PD7 (I/O) / D7 (I/O) / AUDSYNC (I/O)*
PD6 (I/O) / D6 (I/O) / AUDCK (I/O)*
PD5 (I/O) / D5 (I/O) / AUDMD (input)*
PD4 (I/O) / D4 (I/O) / AUDRST (input)*
PD3 (I/O) / D3 (I/O) / AUDATA3 (I/O)*
PD2 (I/O) / D2 (I/O) / SCK2 (I/O) / AUDATA2 (I/O)*
PD1 (I/O) / D1 (I/O) / TXD2 (output) / AUDATA1 (I/O)*
PD0 (I/O) / D0 (I/O) / RXD2 (input) / AUDATA0 (I/O)*
Figure 18.3 Port D
Rev. 2.00, 09/04, page 541 of 720