HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 753
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Item
15.3.16 Mailboxes (MB0
to MB31)
15.3.18 Timer Control
Register (TCR)
15.4.1 Hardware and
Software Resets
•
15.4.2 Initialization after
Hardware Reset
Figure 15.5 Hardware
Reset Flowchart
Figure 15.6 Software
Reset Flowchart
Table 15.5 Setting Range
for TSEG1 and TSEG2 in
BCR
15.4.2 Initialization after
Hardware Reset
Mailbox Transmit/Receive
Settings:
Figure 15.8 Transmission
Flowchart by Event
Trigger
Software Reset
Page
448,
450
449
452
453
455 to
457
460
460
461
462
464
465
466
Revisions (See Manual for Details)
Bits 15, 11, and 6 in the MBx[4] and MBx[5] registers:
Note added.
Bits 13 in the MBx[4] and MBx[5] registers:
Description added.
Bits 15 to 0 in the MBx[6] register:
Description amended.
Note amended.
Note:
Description amended.
Description amended.
These initial settings must be made while the HCAN2 is in
configuration mode. Deleted Configuration mode is a state in
which the GSR3 bit in GSR is set by a reset.
Amended.
Amended.
Note added.
Note added.
*
When MBC = B'001, B'010, B'100, and B'101,
these registers become a local acceptance filter
mask (LAFM) field.
Interrupt to CPU (SLE1)
Clear TXACK
Clear IRR8
IMR8=1?
No
Rev. 2.00, 09/04, page 711 of 720
Yes
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