HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 517

• Manufacturer Part Number: HD64F7047FW40V
• Description: MCU 5V 256K I-TEMP,PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047FW40V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

HCAN2 sleep mode is entered by setting the HCAN2 sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN2 sleep mode is
delayed until the bus becomes idle.
Following flow is recommended to enter sleep mode.
1. Set halt mode (MCR1 = 1).
2. Confirm that the HCAN2 is disconnected from the CAN bus (GSR4 = 1).
3. Clear the source register that controls IRR.
4. Clear halt mode and set bits for sleep mode simultaneously (MCR1 = 0 and MCR5 = 1).
Either of the following methods of clearing HCAN2 sleep mode can be selected:
• Clearing by software
• Clearing by CAN bus operation
11 recessive bits must be received after HCAN2 sleep mode is cleared before CAN bus
communication is re-enabled.
Clearing by Software: HCAN2 sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN Bus Operation: The cancellation method is selected by the MCR7 bit setting
in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an
operation and this change is detected. In this case, the first message is not stored in a mailbox;
messages will be received normally from the second message onward. When a change is detected
on the CAN bus in HCAN2 sleep mode, the bus operation interrupt flag (IRR12) is set in the
interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is
set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
Rev. 2.00, 09/04, page 475 of 720