HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 644
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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3. Normal operation/software standby
23.5.5
The following procedures should be followed.
1. Select the AUD as a pin function by specifying the PFC.
2. Input the clock signal to the AUDCK pin for three cycles at the minimum keeping the
3. Set the AUD reset bit (AUDSRST) in SYSCR to cancel the AUD reset.
Setting the AUDRST pin to the low level and inputting the clock signal to the AUDCK pin can be
done before selection of the AUD as a pin function.
Rev. 2.00, 09/04, page 602 of 720
AUDATA
AUDSRST =
AUDMD
AUDCK
AUDSYNC
AUDRST
AUDATA
AUDRST pin low.
AUD Activation Procedures
(1) AUDMD = high: Input
1
Input
(1) AUDMD = high: Input
(1) AUDMD = high: Input
High-level input
(1) AUDMD = high: Input/Output (2) AUDMD = low: Output
(2) AUDMD = low: High-level Output
(2) AUDMD = low: Output
(2) AUDMD = low: Output
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