HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 580
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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18.1.1
Port A is a 16-bit input/output port. Port A has the following register. For details on register
addresses and register states during each processing, refer to appendix A, Internal I/O Register.
• Port A data register L (PADRL)
18.1.2
The port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data.
Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PADRL, that value is output
directly from the pin, and if PADRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions is a general input, if PADRL is read, the pin state, not the register value, is
returned directly. If a value is written to PADRL, although that value is written into PADRL, it
does not affect the pin state. Table 18.1 summarizes port A data register L read/write operations.
Rev. 2.00, 09/04, page 538 of 720
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
PA15DR
PA14DR
PA13DR
PA12DR
PA11DR
PA10DR
PA9DR
PA8DR
PA7DR
PA6DR
PA5DR
PA4DR
PA3DR
PA2DR
PA1DR
PA0DR
Register Descriptions
Port A Data Register L (PADRL)
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
See table 18.1
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