ATMEGA16M1-AU Atmel, ATMEGA16M1-AU Datasheet - Page 161

• Manufacturer Part Number: ATMEGA16M1-AU
• Description: IC MCU AVR 16K FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

18.5.3
8209D–AVR–11/10
SPSR – SPI Status Register
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the clk
the following table:
Table 18-7.
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
or lower.
The SPI interface on the ATmega16M1/32M1/64M1 is also used for program memory and
EEPROM downloading or uploading. See
programming and verification.
Bit
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
Relationship Between SCK and the Oscillator Frequency
SPIF
R
7
0
Table
WCOL
SPR1
R
6
0
0
0
1
1
0
0
1
1
18-7). This means that the minimum SCK period will be two CPU
R
5
–
0
“Serial Programming Algorithm” on page 303
SPR0
R
4
–
0
0
1
0
1
0
1
0
1
ATmega16M1/32M1/64M1
R
3
–
0
SCK Frequency
f
f
f
f
f
f
f
f
clkio
clkio
clkio
clkio
clkio
clkio
clkio
clkio
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
R
2
–
0
IO
frequency f
R
1
–
0
SPI2X
R/W
0
0
clkio
is shown in
for serial
SPSR
clkio
161
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