ATMEGA16M1-AU Atmel, ATMEGA16M1-AU Datasheet - Page 85

IC MCU AVR 16K FLASH 32TQFP

ATMEGA16M1-AU

Manufacturer Part Number
ATMEGA16M1-AU
Description
IC MCU AVR 16K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16M1-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16M1-AU
Manufacturer:
Atmel
Quantity:
10 000
14. 8-bit Timer/Counter0 with PWM
14.1
14.2
8209D–AVR–11/10
Features
Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in
placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
The PRTIM0 bit in
Timer/Counter0 module.
Figure 14-1. 8-bit Timer/Counter Block Diagram
Two Independent Output Compare Units
Double Buffered Output Compare Registers
Clear Timer on Compare Match (Auto Reload)
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
Timer/Counter
OCRnx
TCCRnA
OCRnx
TCNTn
=
=
“Power Reduction Register” on page 38
“Register Description” on page
direction
count
clear
“Pin Descriptions” on page
TOP
=
TCCRnB
Control Logic
Values
BOTTOM
Fixed
TOP
=
ATmega16M1/32M1/64M1
0
96.
clk
Tn
Generation
Waveform
Generation
Waveform
7. CPU accessible I/O Registers,
must be written to zero to enable
Clock Select
( From Prescaler )
Detector
Edge
Figure
14-1. For the actual
OCnB
(Int.Req.)
OCnB
OCnA
(Int.Req.)
OCnA
TOVn
(Int.Req.)
Tn
85

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