ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 130

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ATA6602/ATA6603
Figure 4-38. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 4-39. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
PSRSYNC
CS10
CS11
CS12
clk
T0
T1
I/O
1. The synchronization logic on the input pins (
Tn
clk
Synchronization
I/O
Synchronization
D
LE
ExtClk
Q
Synchronization
< f
D
clk_I/O
TIMER/COUNTER1 CLOCK SOURCE
0
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
clk
Clear
T1
T1/T0)
10-BIT T/C PRESCALER
CS02
CS00
CS01
is shown in
D
Q
(1)
Edge Detector
TIMER/COUNTER0 CLOCK SOURCE
0
Figure
4-38.
clk
T0
Tn_sync
(To Clock
Select Logic)
clk_I/O
4921E–AUTO–09/09
/2.5.