ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 156

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.14.10.3
156
ATA6602/ATA6603
Timer/Counter1 Control Register C – TCCR1C
Table 4-57.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 5 – Reserved Bit
• Bit 4:3 – WGM13:2: Waveform Generation Mode
• Bit 2:0 – CS12:0: Clock Select
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
Read/Write
Initial Value
CS12
This bit is reserved for future use. For ensuring compatibility with future devices, this bit
must be written to zero when TCCR1B is written.
See TCCR1A Register description.
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
Figure 4-49 on page 151
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to zero
when TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation
unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
0
0
0
0
1
1
1
1
Bit
CS11
0
0
1
1
0
0
1
1
Clock Select Bit Description
FOC1A
R/W
7
0
CS10
FOC1B
0
1
0
1
0
1
0
1
R/W
6
0
and
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
External clock source on T1 pin. Clock on falling edge.
External clock source on T1 pin. Clock on rising edge.
I/O
I/O
I/O
I/O
I/O
Figure 4-50 on page
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R
5
–
0
R
4
–
0
R
3
–
0
151.
R
2
–
0
R
1
–
0
R
0
–
0
4921E–AUTO–09/09
TCCR1C