ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 261

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.20.2
4921E–AUTO–09/09
Analog Comparator Control and Status Register – ACSR
• Bit 7 – ACD: Analog Comparator Disable
• Bit 6 – ACBG: Analog Comparator Bandgap Select
• Bit 5 – ACO: Analog Comparator Output
• Bit 4 – ACI: Analog Comparator Interrupt Flag
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
Initial Value
Read/Write
When this bit is written logic one, the power to the Analog Comparator is switched off. This
bit can be set at any time to turn off the Analog Comparator. This will reduce power con-
sumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator
Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can
occur when the bit is changed.
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the
Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Ana-
log Comparator (see
The output of the Analog Comparator is synchronized and then directly connected to ACO.
The synchronization introduces a delay of 1 - 2 clock cycles.
This bit is set by hardware when a comparator output event triggers the interrupt mode
defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the
ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to
the flag.
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog
Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
When written logic one, this bit enables the input capture function in Timer/Counter1 to be
triggered by the Analog Comparator. The comparator output is in this case directly con-
nected to the input capture front-end logic, making the comparator utilize the noise canceler
and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic
zero, no connection between the Analog Comparator and the input capture function exists.
To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in
the Timer Interrupt Mask Register (TIMSK1) must be set.
These bits determine which comparator events that trigger the Analog Comparator interrupt.
The different settings are shown in
Bit
ACD
R/W
7
0
ACBG
R/W
“Internal Voltage Reference” on page
6
0
ACO
N/A
R
5
Table 4-95 on page
R/W
ACI
4
0
ACIE
R/W
3
0
262.
ATA6602/ATA6603
ACIC
R/W
2
0
71).
ACIS1
R/W
1
0
ACIS0
R/W
0
0
ACSR
261