ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 36

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.7
36
ATA6602/ATA6603
Instruction Execution Timing
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-5
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-5.
Figure 4-6 on page 37
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Initial Value
Read/Write
Bit
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the parallel instruction fetches and instruction executions enabled by the Har-
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
SP15
R/W
SP7
R/W
The Parallel Instruction Fetches and Instruction Executions
15
7
clk
shows the internal timing concept for the Register File. In a single clock
SP14
R/W
R/W
SP6
CPU
14
6
SP13
SP5
R/W
R/W
13
5
CPU
T1
, directly generated from the selected clock source for the
SP12
SP4
R/W
R/W
12
4
SP11
SP3
R/W
R/W
T2
11
3
SP10
R/W
R/W
SP2
10
2
T3
SP1
R/W
R/W
SP9
9
1
SP8
SP0
R/W
R/W
4921E–AUTO–09/09
T4
8
0
SPH
SPL