ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 153

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.14.10
4.14.10.1
4921E–AUTO–09/09
16-bit Timer/Counter Register Description
Timer/Counter1 Control Register A – TCCR1A
Table 4-53.
Table 4-54
PWM mode.
Table 4-54.
Note:
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
Read/Write
Initial Value
COM1A1/COM1B1
COM1A1/COM1B1
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of
the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is
dependent of the WGM13:0 bits setting.
when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Bit
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at TOP. See
Mode” on page 145
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast
COM1A1 COM1A0 COM1B1 COM1B0
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
R/W
7
0
COM1A0/COM1B0
COM1A0/COM1B0
R/W
6
0
for more details.
0
1
0
1
0
1
0
1
R/W
5
0
R/W
Description
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to high
level).
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match,
OC1B disconnected (normal port operation). For all
other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at TOP
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at TOP
4
0
Table 4-53
(1)
R
3
–
0
shows the COM1x1:0 bit functionality
ATA6602/ATA6603
R
2
–
0
WGM11
R/W
1
0
WGM10
R/W
0
0
“Fast PWM
TCCR1A
153