ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 195
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6603P-PLQW
Manufacturer Part Number
ATA6603P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6603P-PLQW.pdf
(360 pages)
Specifications of ATA6603P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL
Quantity:
2 000
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.17.2.3
4.17.2.4
4921E–AUTO–09/09
External Clock
Synchronous Clock Operation
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 4-71. Synchronous Mode XCKn Timing
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As
rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed
at falling XCKn edge and sampled at rising XCKn edge.
f
XCK
f
---------- -
UCPOL = 1
UCPOL = 0
OSC
4
osc
depends on the stability of the system clock source. It is therefore recommended to
Figure 4-70 on page 193
RxD / TxD
RxD / TxD
XCK
XCK
Figure 4-71
shows, when UCPOLn is zero the data will be changed at
for details.
ATA6602/ATA6603
Sample
Sample
195
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