ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 256

MCU W/LIN TXRX REG WTCHDG 48-QFN

ATA6603P-PLQW

Manufacturer Part Number
ATA6603P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6603P-PLQW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL
Quantity:
2 000
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Table 4-93.
256
Status Code
(TWSR)
Prescaler
Bits
are 0
0xA8
0xB0
0xB8
0xC0
0xC8
ATA6602/ATA6603
Status of the 2-wire Serial
Bus and 2-wire Serial
Interface Hardware
Own SLA+R has been
received;
ACK has been returned
Arbitration lost in SLA+R/W as
Master; own SLA+R has been
received; ACK has been
returned
Data byte in TWDR has been
transmitted; ACK has been
received
Data byte in TWDR has been
transmitted; NOT ACK has
been received
Last data byte in TWDR has
been transmitted (TWEA =
“0”); ACK has been received
Status Codes for Slave Transmitter Mode
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action or
Load data byte or
Load data byte or
Load data byte or
No TWDR action
No TWDR action
To/from TWDR
Load data byte
Load data byte
Load data byte
Application Software Response
STA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
STO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
To TWCR
TWINT TWEA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Last data byte will be transmitted and NOT ACK
should be received
Data byte will be transmitted and ACK should be
received
Last data byte will be transmitted and NOT ACK
should be received
Data byte will be transmitted and ACK should be
received
Last data byte will be transmitted and NOT ACK
should be received
Data byte will be transmitted and ACK should be
received
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the
bus becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the
bus becomes free
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the
bus becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the
bus becomes free
4921E–AUTO–09/09

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