ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 60

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.7
60
Power Management and Sleep Modes
ATA6602/ATA6603
Table 4-17.
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See
interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted
for four cycles in addition to the start-up time, executes the interrupt routine, and resumes exe-
cution from the instruction following SLEEP. The contents of the Register File and SRAM are
unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU
wakes up and executes from the Reset Vector.
Figure 4-11 on page 49
distribution. The figure is helpful in selecting an appropriate sleep mode.
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
presents the different clock systems in the ATA6602/ATA6603, and their
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table 4-18 on page 61
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
for a summary. If an enabled
Clock Division Factor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
256
16
32
64
1
2
4
8
4921E–AUTO–09/09