LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 18

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.8 Internal RAM memory
The LPC3141 ROM memory has the following features:
The boot ROM determines the boot mode based on reset state of GPIO0, GPIO1, and
GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins
TRST_N and JTAGSEL must be LOW during power-on reset (see UM10362 JTAG
chapter for details).
LPC3141/3143:
Table 8.
[1]
The ISRAM (Internal Static RAM Memory) controller module is used as controller between
the AHB bus and the internal RAM memory. The internal RAM memory can be used as
working memory for the ARM processor and as temporary storage to execute the code
that is loaded by boot ROM from external devices such as SPI flash, NAND flash, and
SD/MMC cards.
This module has the following features:
Boot mode
NAND
SPI
DFU
SD/MMC
Reserved 0
NOR flash
UART
Test
•
•
•
•
•
Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and
USB (DFU class) interfaces.
Supports option to perform CRC32 checking on the boot image.
Contains pre-defined MMU table (16 kB) for simple systems.
Supports booting from managed NAND devices such as movi-NAND, iNAND,
eMMC-NAND and eSD-NAND using SD/MMC boot mode.
For security reasons this mode is disabled when JTAG security feature is used.
Capacity of 192 kB
LPC3141/3143 boot modes
GPIO0 GPIO1 GPIO2 Description
0
0
0
0
1
1
1
1
All information provided in this document is subject to legal disclaimers.
Table 8
0
0
1
1
0
0
1
1
Rev. 0.16 — 27 May 2010
shows the various boot modes supported on the
0
1
0
1
0
1
0
1
Boots from NAND flash. If proper image is not found,
boot ROM will switch to DFU boot mode.
Boot from SPI NOR flash connected to SPI_CS_OUT0. If
proper image is not found, boot ROM will switch to DFU
boot mode.
Device boots via USB using DFU class specification.
Boot ROM searches all the partitions on the
SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image.
If partition table is missing, it will start searching from
sector 0. A valid image is said to be found if a valid image
header is found, followed by a valid image. If a proper
image is not found, boot ROM will switch to DFU boot
mode.
Reserved for testing.
Boot from parallel NOR flash connected to
EBI_NSTCS_1.
Boot ROM tries to download boot image from UART
((115200 - 8 - n -1) assuming 12 MHz FFAST clock).
Boot ROM is testing ISRAM using memory pattern test.
Switches to UART boot mode on receiving three ASCI
dots ("...") on UART.
[1]
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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