LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 9

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
LPC3141_3143
Preliminary data sheet
Pin name
VSSE_IOC
LCD interface
mLCD_CSB
mLCD_E_RD
mLCD_RS
mLCD_RW_WR
mLCD_DB_0
mLCD_DB_1
mLCD_DB_2
mLCD_DB_3
mLCD_DB_4
mLCD_DB_5
mLCD_DB_6
mLCD_DB_7
mLCD_DB_8
mLCD_DB_9
mLCD_DB_10
mLCD_DB_11
mLCD_DB_12
mLCD_DB_13
mLCD_DB_14
mLCD_DB_15
I
I2SRX_DATA0
I2SRX_DATA1
I2SRX_BCK0
I2SRX_BCK1
I2SRX_WS0
I2SRX_WS1
2
S/digital audio input
[4]
Pin description
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
BGA
Ball
B12;
D6;
D8;
D9;
G11;
L9;
L13
K8
L8
P8
N9
N8
P9
N6
P6
N7
P7
K6
P5
N5
L5
K7
N4
K5
P4
P3
N3
M10
G14
N10
F14
P11
F13
…continued
Digital
I/O
level
[1]
-
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP8
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
All information provided in this document is subject to legal disclaimers.
Application
function
Ground
DO
DO
DO
DO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DI/GPIO
DI/GPIO
DIO/GPIO
DIO/GPIO
DIO/GPIO
DIO/GPIO
Rev. 0.16 — 27 May 2010
Table 10
Pin
state
after
reset
-
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
for pin function selection of multiplexed pins.
[2]
Cell type
[3]
PG1
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
Description
-
LCD chip select (active LOW).
LCD 6800 enable or 8080 read enable
(active HIGH).
LCD instruction register (LOW)/data register
(HIGH) select.
LCD 6800 read/write select or 8080 write
enable (active HIGH).
LCD data 0.
LCD data 1.
LCD data 2.
LCD data 3.
LCD data 4.
LCD data 5.
LCD data 6.
LCD data 7.
LCD data 8/8-bit data 0.
LCD data 9/8-bit data 1.
LCD data 10/8-bit data 2.
LCD data 11/8-bit data 3.
LCD data 12/8-bit data 4/4-bit data 0.
LCD data 13/8-bit data 5/4-bit data 1/serial
clock output.
LCD data 14/8-bit data 6/4-bit data 2/serial
data input.
LCD data 15/8-bit data 7/4-bit data 3/serial
data output.
I
I
I
I
I
I
2
2
2
2
2
2
S serial data receive input.
S serial data receive input.
S bit clock.
S bit clock.
S word select.
S word select.
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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