LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 35

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
Fig 9.
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
EBI_DQM_0_NOE
NAND_NCS_[0:3]
NAND_RYBN[0:3]
Diagram of LCD and MPMC multiplexing
6.28.3 Supply domains
Figure 9
signals are visible.
The EBI unit between the NAND flash interface and the MPMC contains an arbiter that
determines which interface is muxed to the outside world. Both NAND flash and
SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin
arbitration (see
As is shown in
different supply domain than the LCD interface. The EBI control and address signals are
muxed with the LCD interface signals and are part of supply domain SUP8. The
SDRAM/SRAM data lines are shared with the NAND flash through the EBI and are part of
supply domain SUP4. Therefore the following rules apply for connecting memories:
control
control
control
1. SDRAM and bus-based LCD or SRAM: This is the MPMC mode. The supply voltage
3
for SDRAM/SRAM/bus-based LCD and NAND flash must be the same.The dedicated
LCD interface is not available in the MPMC mode.
INTERFACE
only shows the signals that are involved in pad-muxing, so not all interface
FLASH
MPMC
NAND
LCD
Figure 9
All information provided in this document is subject to legal disclaimers.
Section
control
(ALE, CLE)
control
data
LCD_DB_[15:2]
data
LCD_DB_[1:0],
control
data
data
address
Rev. 0.16 — 27 May 2010
6.6).
the EBI (NAND flash/MPMC-control/data) is connected to a
16
16
16
2
EBI
14
6
6
address
EBI_A_[1:0]
data
address
EBI_A_[15:2]
SYSCREG_MUX_LCD_EBI_SEL
16
2
14
(I/O multplexing)
register
1
0
1
0
LPC31xx
SUP4
SUP8
14
2
6
LPC3141/3143
EBI_A_0_ALE
EBI_A_1_CLE
EBI_D_[15:0]
LCD_DB_[15:2] (LCD mode)/
EBI_A_[15:2] (MPMC mode)
LCD_CSB/EBI_NSTCS_0
LCD_DB_1/EBI_NSTCS_1
LCD_DB_0/EBI_CLKOUT
LCD_E_RD/EBI_CKE
LCD_RS/EBI_NDYCS
LCD_RW_WR/EBI_DQM_1
mode
LCD
© NXP B.V. 2010. All rights reserved.
MPMC
mode
002aae157
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