LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 63

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
Table 25.
T
[1]
[2]
[3]
LPC3141_3143
Preliminary data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
SCL
f(o)
r
f
BUF
LOW
HD;STA
HIGH
SU;DAT
SU;STA
SU;STO
amb
Parameters are valid over operating temperature range unless otherwise specified.
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
Bus capacitance C
=
−
40
°
Dynamic characteristic: I
C to +85
9.8 I
Parameter
SCL clock frequency
output fall time
rise time
fall time
bus free time between a STOP and
START condition
LOW period of the SCL clock
hold time (repeated) START
condition
HIGH period of the SCL clock
data set-up time
set-up time for a repeated START
condition
set-up time for STOP condition
b
°
C.
in pF, from 10 pF to 400 pF.
[1]
2
Fig 26. I
C-bus
I2SRX_SCK
I2SRX_SDA
I2SRX_WS
2
S-bus timing (input)
2
C-bus pins
All information provided in this document is subject to legal disclaimers.
Rev. 0.16 — 27 May 2010
t
WH
Conditions
Standard mode
Fast mode
V
Standard mode
Fast mode
Standard mode
Fast mode
-
Standard mode
Fast mode
-
Standard mode
Fast mode
Standard mode
Fast mode
-
Standard mode
Fast mode
IH
to V
T
cy
IL
t
WL
t
su(D)
t
su(D)
0
<tbd>
<tbd>
4.0
250
4.0
Min
0
20 + 0.1 × C
20 + 0.1 × C
20 + 0.1 × C
<tbd>
4.7
1.3
<tbd>
0.6
100
<tbd>
0.6
t
t
hD)
h2
b
b
b
[3]
[3]
[3]
LPC3141/3143
t
Typ
<tbd>
<tbd>
-
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
f
[2]
© NXP B.V. 2010. All rights reserved.
Max
100
400
-
1000
300
300
300
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
t
r
002aad993
63 of 74
Unit
kHz
kHz
ns
ns
ns
ns
ns
μs
μs
μs
μs
ns
ns
μs
μs