W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet

no-image

W78E052DDG

Manufacturer Part Number
W78E052DDG
Description
IC MCU 8-BIT 8K FLASH 40-DIP
Manufacturer
Nuvoton Technology Corporation of America
Series
W78r
Datasheet

Specifications of W78E052DDG

Core Processor
8052
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
36
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W78E052DDG
Manufacturer:
NUVOTON
Quantity:
1 000
Part Number:
W78E052DDG
Manufacturer:
Winbond
Quantity:
1 000
Table of Contents-
1
2
3
4
5
6
7
8
9
10
11
12
13
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES ................................................................................................................................. 5
PARTS INFORMATION LIST ..................................................................................................... 6
3.1
PIN CONFIGURATIONS............................................................................................................. 7
PIN DESCRIPTIONS .................................................................................................................. 9
BLOCK DIAGRAM .................................................................................................................... 11
FUNCTIONAL DESCRIPTION.................................................................................................. 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
MEMORY ORGANIZATION...................................................................................................... 14
8.1
8.2
SPECIAL FUNCTION REGISTERS ......................................................................................... 18
9.1
INSTRUCTION.......................................................................................................................... 35
INSTRUCTION TIMING ............................................................................................................ 43
POWER MANAGEMENT.......................................................................................................... 44
12.1
12.2
RESET CONDITIONS............................................................................................................... 45
13.1
Lead Free (RoHS) Parts information list......................................................................... 6
On-Chip Flash EPROM ................................................................................................ 12
I/O Ports........................................................................................................................ 12
Serial I/O ....................................................................................................................... 12
Timers ........................................................................................................................... 12
Interrupts....................................................................................................................... 12
Data Pointers ................................................................................................................ 13
Architecture................................................................................................................... 13
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
Program Memory (on-chip Flash) ................................................................................. 14
Scratch-pad RAM and Register Map ............................................................................ 14
8.2.1
8.2.2
8.2.3
SFR Detail Bit Descriptions .......................................................................................... 20
Idle Mode ...................................................................................................................... 44
Power Down Mode ....................................................................................................... 44
Sources of reset............................................................................................................ 45
13.1.1
13.1.2
ALU ................................................................................................................................13
Accumulator ...................................................................................................................13
B Register.......................................................................................................................13
Program Status Word .....................................................................................................13
Scratch-pad RAM ...........................................................................................................13
Stack Pointer ..................................................................................................................13
Working Registers ..........................................................................................................16
Bit addressable Locations ..............................................................................................17
Stack ..............................................................................................................................17
External Reset ..............................................................................................................45
Software Reset .............................................................................................................45
W78E054D/W78E052D/W78E051D Data Sheet
8-BIT MICROCONTROLLER
- 1 -
Publication Release Date: Dec 29, 2009
Revision A09

Related parts for W78E052DDG

W78E052DDG Summary of contents

Page 1

Table of Contents- 1 GENERAL DESCRIPTION ......................................................................................................... 4 2 FEATURES ................................................................................................................................. 5 3 PARTS INFORMATION LIST ..................................................................................................... 6 3.1 Lead Free (RoHS) Parts information list......................................................................... 6 4 PIN CONFIGURATIONS............................................................................................................. 7 5 PIN DESCRIPTIONS .................................................................................................................. 9 6 BLOCK DIAGRAM .................................................................................................................... 11 ...

Page 2

Watchdog Timer Reset.................................................................................................45 13.1.4 RESET STATE .............................................................................................................45 13.2 Interrupts....................................................................................................................... 46 13.3 Interrupt Sources .......................................................................................................... 46 13.4 Priority Level Structure ................................................................................................. 46 13.5 Interrupt Response Time .............................................................................................. 48 13.6 Interrupt Inputs.............................................................................................................. 49 14 PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 50 14.1 Timer/Counters 0 ...

Page 3

PACKAGE DIMENSIONS ......................................................................................................... 78 22.1 40-pin DIP ..................................................................................................................... 78 22.2 44-pin PLCC ................................................................................................................. 79 22.3 44-pin PQFP ................................................................................................................. 80 22.4 48-pin LQFP.................................................................................................................. 81 23 REVISION HISTORY ................................................................................................................ 88 W78E054D/W78E052D/W78E051D Data Sheet Publication Release Date: Dec 29, 2009 - 3 ...

Page 4

GENERAL DESCRIPTION The W78E054D/W78E052D/W78E051D series is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. The instruction set for the W78E054D/ W78E052D/ W78E051D series is fully compatible with the standard 8052. The W78E054D/W78E052D/W78E051D series ...

Page 5

... Lead Free (RoHS) LQFP 48: - Lead Free (RoHS) DIP 40: - Lead Free (RoHS) PLCC 44: - Lead Free (RoHS) PQFP 44: - Lead Free (RoHS) LQFP 48: W78E054D/W78E052D/W78E051D Data Sheet W78E054DDG W78E054DPG W78E054DFG W78E054DLG W78E052DDG W78E052DPG W78E052DFG W78E052DLG W78E051DDG W78E051DPG W78E051DFG W78E051DLG Publication Release Date: Dec 29, 2009 - 5 - Revision A09 ...

Page 6

... PARTS INFORMATION LIST 3.1 Lead Free (RoHS) Parts information list Table 3-1: Lead Free (RoHS) Parts information list LD FLASH PART NO. RAM W78E054DDG W78E054DPG W78E054DFG W78E054DLG 256 Bytes W78E052DDG W78E052DPG W78E052DFG W78E052DLG W78E051DDG W78E051DPG W78E051DFG W78E051DLG W78E054D/W78E052D/W78E051D Data Sheet AP FLASH PACKAGE SIZE SIZE ...

Page 7

PIN CONFIGURATIONS W78E054D/W78E052D/W78E051D Data Sheet Publication Release Date: Dec 29, 2009 - 7 - Revision A09 ...

Page 8

W78E054D/W78E052D/W78E051D Data Sheet P1 P1.7 4 RST RXD, P3.0 5 PQFP 44-pin INT2, P4 TXD, P3.1 INT0, P3.2 8 INT1, P3 T0, P3.4 T1, P3 P1.5 2 P1.6 P1.7 3 ...

Page 9

PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address I EA and data will not be present ...

Page 10

Pin Description, continued SYMBOL TYPE DESCRIPTIONS PORT 3: Port bi-directional I/O port with internal pull-ups. All bits have al- ternate functions, which are described below: RXD (P3.0): Serial Port 0 input TXD (P3.1): Serial Port 0 output ...

Page 11

BLOCK DIAGRAM Figure 6- 1 W78E054D/W78E052D/W78E051D Block Diagram W78E054D/W78E052D/W78E051D Data Sheet Publication Release Date: Dec 29, 2009 - 11 - Revision A09 ...

Page 12

FUNCTIONAL DESCRIPTION The W78E054D/W78E052D/W78E051D series architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 16K/8K/4K flash EPROM, 2K FLASH EPROM for ISP function, 256 bytes of RAM, three timer/counters, and a serial port. ...

Page 13

Data Pointers The data pointer of W78E054D/W78E052D/W78E051D series is same as standard 8052 that have one 16-bit Data Pointer (DPTR). 7.7 Architecture The W78E054D/W78E052D/W78E051D series are based on the standard 8052 device built around an 8-bit ALU ...

Page 14

MEMORY ORGANIZATION The W78E054D/W78E052D/W78E051D series separate the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op- codes, while the Data Memory is used to store data ...

Page 15

Figure 8- 2 W78E054D/W78E052D/W78E051D RAM and SFR Memory Map Since the scratch-pad RAM is only 256bytes it can be used only when data contents are small. There are several other special purpose areas within the scratch-pad RAM. These are illustrated ...

Page 16

FFH 80H 7FH 30H 2FH 7F 2EH 77 2DH 6F 2CH 67 2BH 5F 2AH 57 29H 4F 28H 47 27H 3F 26H 37 25H 2F 24H 27 23H 1F 22H 17 21H 0F 20H 07 1FH 18H 17H 10H ...

Page 17

Bit addressable Locations The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit addressable. This means that a bit in this area can be individually addressed. In addition some of the SFRs are also ...

Page 18

SPECIAL FUNCTION REGISTERS The W78E054D/W78E052D/W78E051D series uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are ac- cessed by direct addressing only. Some of the SFRs ...

Page 19

Special Function Registers: SYMBOL DEFINITION ADDRESS MSB B B register F0H ACC Accumulator E0H P4 Port 4 D8H PSW Program status word D0H TH2 T2 reg. high CDH TL2 T2 reg. low CCH RCAP2H T2 capture low CBH RCAP2L T2 ...

Page 20

DPL Data pointer low 82H SP Stack pointer 81H P0 Port 0 80H 9.1 SFR Detail Bit Descriptions Port 0 Bit P0.7 P0.6 P0.5 Mnemonic: P0 BIT NAME FUNCTION 7-0 P0.[7:0] Port open-drain bi-directional ...

Page 21

Mnemonic: P0UPR BIT NAME FUNCTION 0 P0UP 0: Port 0 pins are open-drain. 1: Port 0 pins are internally pulled-up. Port 0 is structurally the same as Port 2. Power Control Bit SMOD SMOD0 ...

Page 22

TR0 Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter on or off. 3 IE1 Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on INT . This bit ...

Page 23

Timer/Counter 1 is stopped. Timer 0 LSB Bit TL0.7 TL0.6 TL0.5 Mnemonic: TL0 BIT NAME FUNCTION 7-0 TL0.[7:0] Timer 0 LSB. Timer 1 LSB Bit TL1.7 TL1.6 TL1.5 Mnemonic: TL1 BIT NAME FUNCTION 7-0 ...

Page 24

BIT NAME FUNCTION 0 ALE_OFF 1: Disenable ALE output 0: Enable ALE output Watchdog Timer Control Register Bit ENW CLRW WIDL Mnemonic: WDTC BIT NAME FUNCTION 7 ENW Enable watch-dog if set. 6 CLRW Clear watch-dog timer ...

Page 25

Mnemonic: SCON BIT NAME FUNCTION 7 SM0/FE Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is described below. ...

Page 26

BIT NAME FUNCTION 7~0 SBUF Serial data on the serial port is read from or written to this location. It actually consists of two separate internal 8-bit registers. One is the receive resister, and the other is the transmit buffer. ...

Page 27

P3.3 INT1 2 P3.2 INT0 1 P3 P3.0 RX Interrupt High Priority Bit IPH.7 IPH.6 IPH.5 Mnemonic: IPH BIT NAME FUNCTION 7 IPH.7 1: Interrupt ...

Page 28

EAPAGE ERASE PAGE Operation Modes Bit Mnemonic: EAPAGE BIT NAME FUNCTION 1 EAPG1 1.To ease PAGE1 when ease command is set.(LD flash) 0 EAPG0 1.To ease PAGE0 when ease command is set. (AP Flash) ...

Page 29

SWRST - - Mnemonic: CHPCON Bit Name Function 7 SWRST When this bit is set to 1, and both FBOOTSL and ENP are set will enforce microcontroller reset to initial condition just like power on reset. This ...

Page 30

Mnemonic: SFRAL BIT NAME FUNCTION 7-0 SFRAL.[7:0] The programming address of on-chip flash memory in programming mode. SFRFAL contains the low-order byte of address. SFR program of address high Bit SFRAH.7 SFRAH.6 SFRAH.5 Mnemonic: SFRAH BIT NAME ...

Page 31

Program Verify APROM 0 Read APROM 0 Timer 2 Control Bit TF2 EXF2 RCLK Mnemonic: T2CON BIT NAME FUNCTION 7 TF2 Timer 2 overflow flag: This bit is set when Timer 2 overflows also set ...

Page 32

Timer 2 Mode Control Bit Mnemonic: T2MOD BIT NAME FUNCTION 0 DCEN Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that timer 2 counts in 16-bit auto-reload mode. Timer ...

Page 33

BIT NAME FUNCTION 7-0 TH2.[7:0] Timer 2 MSB Program Status Word Bit Mnemonic: PSW BIT NAME FUNCTION 7 CY Carry flag: Set for an arithmetic operation which results in a carry being generated from ...

Page 34

ACC The A or ACC register is the standard 8052 accumulator. B Register Bit B.7 B.6 B.5 Mnemonic: B Bit Name Function 7-0 B The B register is the standard 8052 register that serves as a ...

Page 35

INSTRUCTION The W78E054D/W78E052D/W78E051D series execute all the instructions of the standard 8052 fam- ily. The operations of these instructions, as well as their effects on flag and status bits, are exactly the same. Op-code NOP ADD A, R0 ADD ...

Page 36

W78E054D/W78E052D/W78E051D Data Sheet Op-code HEX Code Bytes SUBB SUBB SUBB SUBB SUBB SUBB A, @R0 96 SUBB A, @R1 97 SUBB A, direct 95 SUBB ...

Page 37

W78E054D/W78E052D/W78E051D Data Sheet Op-code HEX Code DEC @R1 17 DEC direct 15 MUL AB A4 DIV ANL ANL ANL ANL ANL A, R4 ...

Page 38

W78E054D/W78E052D/W78E051D Data Sheet Op-code HEX Code ORL direct, #data 43 XRL XRL XRL XRL XRL XRL XRL XRL A, ...

Page 39

W78E054D/W78E052D/W78E051D Data Sheet Op-code HEX Code MOV A, direct E5 MOV A, #data 74 MOV R0 MOV R1 MOV R2 MOV R3 MOV R4 MOV R5 MOV R6, ...

Page 40

W78E054D/W78E052D/W78E051D Data Sheet Op-code HEX Code MOV direct MOV direct MOV direct MOV direct MOV direct MOV direct MOV direct MOV direct MOV direct, ...

Page 41

W78E054D/W78E052D/W78E051D Data Sheet Op-code HEX Code Bytes XCH A, @R0 C6 XCH A, @R1 C7 XCHD A, @R0 D6 XCHD A, @R1 D7 XCH A, direct C5 CLR C C3 CLR bit C2 SETB C D3 SETB bit D2 CPL ...

Page 42

W78E054D/W78E052D/W78E051D Data Sheet Op-code HEX Code JB bit, rel 20 JNB bit, rel 30 JBC bit, rel 10 CJNE A, direct, rel B5 CJNE A, #data, rel B4 CJNE @R0, #data, rel B6 CJNE @R1, #data, rel B7 CJNE R0, ...

Page 43

INSTRUCTION TIMING A machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts for two oscillator periods. Thus a machine cycle takes 12 oscillator periods or 1us if the oscillator fre- quency ...

Page 44

POWER MANAGEMENT The W78E054D/W78E052D/W78E051D has several features that help the user to control the power consumption of the device. The power saved features have basically the POWER DOWN mode and the IDLE mode of operation. 12.1 Idle Mode The ...

Page 45

RESET CONDITIONS The user has several hardware related options for placing the W78E054D/W78E052D/W78E051D into reset condition. In general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state ...

Page 46

Interrupts The W78E054D/W78E052D/W78E051D has a 4 priority level interrupt structure with 8 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or ...

Page 47

PRIORITY BITS IPH XICON.7/ XICON The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled inter- rupts are polled and their priority is resolved. If certain conditions are met then the ...

Page 48

Each interrupt source can be individually programmed to one of 2 priority levels by setting or clearing bits in the IP registers. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another ...

Page 49

If the polling cycle is not the last machine cycle of the instruc- tion being executed, then an additional delay is introduced. The maximum response time (if no other interrupt is in service) occurs if ...

Page 50

PROGRAMMABLE TIMERS/COUNTERS The W78E054D/W78E052D/W78E051D series have Three 16-bit programmable timer/counters. A machine cycle equals oscillator periods, and it depends on 12T mode or 6T mode that the user configured this device. 14.1 Timer/Counters 0 & 1 ...

Page 51

The selection of the time-base in the timer mode is similar to that in Mode 0. The gate function operates similarly to that in Mode 0. Fosc 1/12 T0=P3.4 (T1=P3.5) TR0=TCON.4 (TR1=TCON.6) GATE=TMOD.3 (GATE=TMOD.7) INT0=P3.2 ...

Page 52

C/ , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12 control bits 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle counter (clock/12) ...

Page 53

Figure 14- 4 16-Bit Capture Mode 14.3.2 Auto-Reload Mode, Counting up The auto-reload mode counter is enabled by clearing the CP RL and clearing the DCEN bit in T2MOD(bit0) register. In this mode, Timer/Counter ...

Page 54

Figure 14- 6 16-Bit Auto-reload Mode, Counting Up 14.3.4 Baud Rate Generator Mode The baud rate generator mode is enabled by setting either the RCLK or TCLK bits in T2CON register. While in the baud rate generator mode, Timer/Counter ...

Page 55

WATCHDOG TIMER The Watchdog timer is a free-running timer which can be programmed by the user to serve as a sys- tem monitor, a time-base generator or an event timer basically a set of dividers that divide ...

Page 56

Figure 15- 1 Watchdog Timer Block Diagram Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 Table 15- 1 Watch-Dog time-out ...

Page 57

SERIAL PORT Serial port in this device is a full duplex port. The serial port is capable of synchronous as well as asynchronous communication. In Synchronous mode the device generates the clock and operates in a half duplex mode. ...

Page 58

Figure 16- 1 Serial port mode 0 The TI flag is set high in S6P2 following the end of transmission of the last bit. The serial port will re- ceive data when REN is 1 and RI is zero. The ...

Page 59

The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. ...

Page 60

SMOD bit in PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at S6P2 following the ...

Page 61

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes ...

Page 62

FLASH ROM CODE BOOT MODE SELECTION The W78E054D/W78E052D/W78E051D boots from APROM program (16K/8K/4K bytes) or LDROM program (2K bytes) at power on reset or external reset. BOOT MODE Select by CONFIG bits Config boot select at Power-on reset and ...

Page 63

ISP(IN-SYSTEM PROGRAMMING) ISP is the ability of program MCU to be programmed while F/W code in AP-ROM or LD-ROM. (Note: Timer 0 for program, erase, read on ISP mode. ISP operation voltage 3.3- 5.5V) START Enter In-System Programming Mode ...

Page 64

W78E054D/W78E052D/W78E051D Data Sheet GO Timer Interrupt Service Routine: Stop Timer & disable interrupt NO Is F02K BOOT Mode? YES Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) Setting erase operation mode: MOV ERPAGE,#02H MOV ...

Page 65

W78E054D/W78E052D/W78E051D Data Sheet PGM Read_Compay_ID YES OV SFRCN,#0Bh End of Programming ? MOV CHPCON,#03h NO Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) Read_Device_ID MOV SFRCN,#0Ch MOV CHPCON,#03h Get the parameters of new code (Address ...

Page 66

W78E054D/W78E052D/W78E051D Data Sheet PGM Read_Compay_ID YES End of Programming ? NO Setting Timer and enable Timer interrupt for wake-up . F02K BOOT Mode ? (50us for program operation) Get the parameters of new code (Address and data bytes) Software reset ...

Page 67

CONFIG BITS During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and veri- fied repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM ...

Page 68

Bit 0: Lock bits 0: Lock enable 1: Lock disable This bit is used to protect the customer's program code in the W78E054D/W78E052D/W78E051D. It may be set after the programmer finishes the programming and verifies sequence. Once these bits are ...

Page 69

... P3.5/T1 P2.5 10uF 27 P2 P2.7 P1.0/T2 2 P1.1/T2EX 3 P1 P1.3 WR/P3 8.2K P1.4 RD/P3 P1.5 PSEN 7 30 P1.6 ALE 8 11 P1.7 TXD/P3.1 10 RXD/P3.0 W78E054DDG-40DIP W78E052DDG-40DIP W78E051DDG-40DIP Figure B W78E054D/W78E052D/W78E051D Data Sheet AD0 AD0 AD1 AD1 AD2 AD2 AD3 AD3 AD4 AD4 A4 35 ...

Page 70

ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings SYMBOL PARAMETER DC Power Supply V DD Input Voltage V IN Operating Temperature T A (W78E054D/W78E052D/W78 E051D) Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely af- fects the ...

Page 71

DC ELECTRICAL CHARACTERISTICS T =-40℃~+85℃, V =2.4V~5.5V Sym Parameter Input Low Voltage V 2.4 < V (Ports 0~4, /EA, XTAL1, IL RST) Input High Voltage V 2.4 < (Ports 0~4, /EA) Input High Voltage ...

Page 72

Typical values are not guaranteed. The values listed are tested at room temperature and based on a limited number of samples. *2: Pins of ports 1~4 source a transition current when they are being externally driven from 1 to ...

Page 73

There are no duty cycle requirements on the XTAL1 input. 21.3.2 Program Fetch Cycle PARAMETER Address Valid to ALE Low Address Hold from ALE Low PSEN ALE Low to Low PSEN Low to Data Valid Data Hold after PSEN ...

Page 74

Data Write Cycle PARAMETER SYMBOL Tdaw ALE Low to WR Low Tdad Data Valid to WR Low Tdwd Data Hold from WR High Tdwr WR Pulse Width Note: "Δ" (due to buffer driving delay and wire loading ...

Page 75

TIMING waveforms 21.4.1 Program Fetch Cycle XTAL1 ALE T APL PSEN T PSW T AAS PORT 2 T PDA T AAH PORT 0 A0-A7 Code 21.4.2 Data Read Cycle XTAL1 ALE PSEN PORT ...

Page 76

Data Write Cycle XTAL1 ALE PSEN PORT 2 PORT 0 A0- DAW 21.4.4 Port Access Cycle S5 XTAL1 ALE T PDS PORT INPUT SAMPLE W78E054D/W78E052D/W78E051D Data Sheet A8-A15 ...

Page 77

Reset Pin Access Cycle W78E054D/W78E052D/W78E051D Data Sheet Publication Release Date: Dec 29, 2009 - 77 - Revision A09 ...

Page 78

PACKAGE DIMENSIONS 22.1 40-pin DIP Dimension in inch Dimension in mm Symbol Min Nom Max A A 0.010 1 A 0.150 2 B 0.016 B 0.048 ...

Page 79

PLCC Seating Plane G D Dimension in inch Symbol Min A A 0.020 1 A 0.145 2 b 0.026 1 b 0.016 c 0.008 D 0.648 E 0.648 ...

Page 80

PQFP See Detail F Seating Plane Dimension in inch Symbol Min A A 0.002 1 A 0.075 2 b 0.01 c 0.004 D 0.390 E 0.390 e H 0.510 ...

Page 81

LQFP W78E054D/W78E052D/W78E051D Data Sheet Publication Release Date: Dec 29, 2009 - 81 - Revision A09 ...

Page 82

Application Note: In-system Programming Software Examples This application note illustrates the in-system programmability of the microcontroller. In this example, microcontroller will boot from 2K LDROM bank enter in-system programming mode for programming the contents of APROM, this sample to Erase ...

Page 83

SP,#060h mov TMOD,#01h ;Set Timer0 as mode1 call Read_Company_ID call Read_Device_ID_HIGH call Read_Device_ID_LOW call Erase_APROM call Erase_Verify_ROM call Program_APROM call Program_Verify_APROM call Software_Reset sjmp $ ;************************************************************************ ; * Read_Company_ID ;************************************************************************ Read_Company_ID: mov SFRCN,#READ_CID mov TL0,#LOW (65536-READ_TIME) mov TH0,#HIGH(65536-READ_TIME) setb ...

Page 84

CHPCON,#00000011b clr TF0 clr TR0 mov A,SFRFD ;read device id high byte ret ;***************************************************************************** ; * read device ID low ;************************************************************************ Read_Device_ID_LOW: mov SFRAL,#0FEh mov SFRAH,#0FFh mov SFRCN,#READ_DID mov TL0,#LOW (65536-READ_TIME) mov TH0,#HIGH(65536-READ_TIME) setb TR0 mov CHPCON,#00000011b clr TF0 ...

Page 85

TL0,#LOW (65536-ERASE_TIME) mov TH0,#HIGH(65536-ERASE_TIME) setb TR0 mov CHPCON,#00000011b mov EAPAGE,#00h ;clear EAPAGE clr TF0 clr TR0 ret ;************************************************************************ ; * VERIFY APROM BANK ;************************************************************************ Erase_Verify_ROM: mov SFRCN,#ERASE_VERIFY mov DPTR,#0000h er_lp: mov TL0,#LOW (65536-READ_TIME) mov TH0,#HIGH(65536-READ_TIME) mov SFRAL,DPL mov SFRAH,DPH ...

Page 86

SFRCN,#PROGRAM_ROM mov DPTR,#0000h mov A,#055h wr_lp: mov TH0,#HIGH(65536-PROGRAM_TIME) mov TL0,#LOW (65536-PROGRAM_TIME) mov SFRFD,A mov SFRAL,DPL mov SFRAH,DPH setb TR0 mov CHPCON,#00000011b clr TF0 clr TR0 cpl A inc DPTR mov R0,DPL cjne R0,#LOW (APROM_END_ADDRESS),wr_lp mov R1,DPH cjne R1,#HIGH(APROM_END_ADDRESS),wr_lp ret ...

Page 87

A mov B,A inc DPTR mov R0,DPL cjne R0,#LOW (APROM_END_ADDRESS),rd_lp mov R1,DPH cjne R1,#HIGH(APROM_END_ADDRESS),rd_lp ret Program_Fail: mov P1,#03h sjmp $ ;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU TO APROM ;****************************************************************************** Software_Reset: MOV CHPCON,#081h ;CHPCON=081h, SOFTWARE RESET to APROM. ;****************************************************************************** ...

Page 88

REVISION HISTORY VERSION DATE PAGE August 14, A01 - 2008 November A02 - 3,2008 December A03 - 15,2008 January A04 70 7,2007 A05 March 9, 2009 43 18 March 20, A06 - 2009 - A07 April 22, 2009 68 ...

Page 89

Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instru- ments, airplane or spaceship instruments, transportation instruments, traffic signal instru- ments, combustion control instruments, or ...

Related keywords