W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 55

• Manufacturer Part Number: W78E052DDG
• Description: IC MCU 8-BIT 8K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E052DDG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

15 WATCHDOG TIMER
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a sys-
tem monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values de-
pending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should
restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog
timer are discussed below.
ENW : Enable watchdog if set.
CLRW : Clear watchdog timer and Pre-scalar if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watchdog is disabled un-
der IDLE mode. Default is cleared.
PS2, PS1, PS0: Watchdog Pre-scalar timer select. Pre-scalar is selected when set PS2−0 as follows:
The time-out period is obtained using the following equation for 12T per machine cycle:
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, Pre-scalar and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
PS2 PS1 PS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
OSC
0
1
0
1
0
1
0
1
1
×
2
W78E054D/W78E052D/W78E051D Data Sheet
14
×
Pre-scalar select
Pr
e
−
- 55 -
scalar
128
256
16
32
64
2
8
4
×
1000
×
Publication Release Date: Dec 29, 2009
12
ms
Revision A09