W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 68

• Manufacturer Part Number: W78E052DDG
• Description: IC MCU 8-BIT 8K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E052DDG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

W78E054D/W78E052D/W78E051D Data Sheet
Bit 0: Lock bits
0: Lock enable
1: Lock disable
This bit is used to protect the customer's program code in the W78E054D/W78E052D/W78E051D. It
may be set after the programmer finishes the programming and verifies sequence. Once these bits are
set to logic 0, both the FLASH data and Special Setting Registers can not be accessed again.
Bit 1:MOVC inhibit
0: MOVC inhibit enable
1: MOVC inhibit disable
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC in-
struction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
Bit 2: CBS
Config boot select at Power-on reset and external reset.
CBS=1: Boot from AP Flash block (default).
CBS=0: Boot from LD Flash block (0x3800).
Bit 3: NSR (Noise Sensitivity Reduction)
NSR=1: Noise Sensitivity Reduction is disabled.
NSR=0: Noise Sensitivity Reduction is enabled.
Bit 4: Must be “1”
Bit 5: Machine Cycle Select
This bit is select MCU core, default value is logic 1, the MCU core is 12T per instruction. Once this bit
is set to logic 0, the MCU core is 6T per instruction.
Bit 6: Must be “1”
Bit 7: Crystal Select
0 (24MHz): If system clock is slower than 24MHz, programming “0”. It can reduce EMI effect and save
the power consumption.
1 (40MHz): If system clock is faster than 24MHz, programming “1”.
- 68 -