W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 48

• Manufacturer Part Number: W78E052DDG
• Description: IC MCU 8-BIT 8K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E052DDG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Each interrupt source can be individually programmed to one of 2 priority levels by setting or clearing
bits in the IP registers. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. So, if two requests of different priority levels are
received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence deter-
mines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking
is only used to resolve simultaneous requests of the same priority level.
Table below summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and External interrupt may wake up the CPU from Power Down mode.
Source
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Timer 2 Over-
flow/Match
External Interrupt 2
External Interrupt 3
13.5 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the in-
terrupt and the instruction underway. In the case of external interrupts INT0 and INT1 , they are sam-
pled at S5P2 of every machine cycle and then their corresponding interrupt flags IEx will be set or re-
set. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has oc-
curred. These flag values are polled only in the next machine cycle. If a request is active and all three
conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes four ma-
chine cycles to be completed. Thus there is a minimum time of five machine cycles between the inter-
rupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
Flag
IE0
TF0
IE1
TF1
RI +
TI
TF2
IE2
IE3
Vector
address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
Table 13- 2 Summary of interrupt sources
Enable bit
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
ET2 (IE.5)
EX2
(XICON.2)
EX3
(XICON.6)
W78E054D/W78E052D/W78E051D Data Sheet
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Interrupt
Priority
IPH.0, IP.0
IPH.1, IP.1
IPH.2, IP.2
IPH.3, IP.3
IPH.4, IP.4
IPH.5, IP.5
IPH.6,
PX2
IPH.7,
PX3
Flag cleared
by
Hardware,
software
Hardware,
software
Hardware,
software
Hardware,
software
Software
Software
Hardware,
software
Hardware,
software
Arbitration
ranking
1(highest)
2
3
4
5
6
7
8(lowest)
Power-
down
wakeup
Yes
No
Yes
No
No
No
Yes
Yes