W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 45

• Manufacturer Part Number: W78E052DDG
• Description: IC MCU 8-BIT 8K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E052DDG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

W78E054D/W78E052D/W78E051D Data Sheet
13 RESET CONDITIONS
The user has several hardware related options for placing the W78E054D/W78E052D/W78E051D into
reset condition. In general, most register bits go to their reset value irrespective of the reset condition,
but there are a few flags whose state depends on the source of reset. The user can use these flags to
determine the cause of reset using software.
13.1 Sources of reset
13.1.1 External Reset
The device continuously samples the RST pin at state S5P2 of every machine cycle. Therefore the
RST pin must be held for at least 2 machine cycles (24 clock cycles) to ensure detection of a valid
RST high. The reset circuitry then synchronously applies the internal reset signal. Thus the reset is a
synchronous operation and requires the clock to be running to cause an external reset. For more tim-
ing information, please reference the character 21.4.5 (Page 77).
Once the device is in reset condition, it will remain so as long as RST is 1. Even after RST is deacti-
vated, the device will continue to be in reset state for up to two machine cycles, and then begin pro-
gram execution from 0000h. There is no flag associated with the external reset condition.
13.1.2 Software Reset
The W78E054D/W78E052D/W78E051D offers a software reset to switch back to the AP Flash
EPROM. Setting CHPCON bits 0, 1 and 7 to logic-1 creates software reset to reset the CPU to start
APROM code. Note: Software Reset only LDROM jump to APROM, APROM can’t software reset to
LDROM.
13.1.3 Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear
the watchdog timer at any time, causing it to restart the count. When the time-out interval is reached
an interrupt flag is set. If the Watchdog reset is enabled and the watchdog timer is not cleared, the
watchdog timer will generate a reset. This places the device into the reset condition. The reset condi-
tion is maintained by hardware for two machine cycles. Once the reset is removed the device will be-
gin execution from 0000h.
13.1.4 RESET STATE
Most of the SFRs and registers on the device will go to the same condition in the reset state. The Pro-
gram Counter is forced to 0000h and is held there as long as the reset condition is applied. However,
the reset state does not affect the on-chip RAM. The data in the RAM will be preserved during the re-
set. However, the stack pointer is reset to 07h, and therefore the stack contents will be lost. The RAM
contents will be lost if the VDD falls below approximately 2V, as this is the minimum voltage level re-
quired for the RAM to operate normally. Therefore after a first time power on reset the RAM contents
will be indeterminate. During a power fail condition, if the power falls below 2V, the RAM contents are
lost.
After a reset most SFRs are cleared. Interrupts and Timers are disabled. The Watchdog timer is dis-
abled if the reset source was a POR. The port SFRs have 0FFh written into them which puts the port
pins in a high state.
Publication Release Date: Dec 29, 2009
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Revision A09