ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 113

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
Note:
Table 41.
Address
(Hex.)
0C
0D
0E
Reset Value
Reset Value
Reset Value
Bit 6 = ICF Input capture flag
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection bit
Bit 4 = TB1IE Timebase Interrupt enable bit
Bit 3 = TB1F Timebase Interrupt flag
Bits 2:0 = Reserved, must be kept cleared.
Lite timer input capture register (LTICR)
Reset value: 0000 0000 (00h)
Bits 7:0 = ICR[7:0] Input Capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling
edge occurs on the LTIC pin.
Lite timer register mapping and reset values
Register
LTCSR2
LTCNTR
LTARR
label
ICR7
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No Input Capture
1: An Input Capture has occurred
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
7
CNT7
AR7
ICR6
7
0
0
0
CNT6
AR6
6
0
0
0
ICR5
OSC
OSC
* 8000 (1 ms @ 8 MHz)
* 16000 (2 ms @ 8 MHz)
CNT5
AR5
5
0
0
0
ICR4
Read only
CNT4
AR4
4
0
0
0
ICR3
CNT3
AR3
3
0
0
0
ICR2
CNT2
AR2
2
0
0
0
On-chip peripherals
ICR1
TB2IE
CNT1
AR1
1
0
0
0
ICR0
CNT0
TB2F
113/245
AR0
0
0
0
0
0