ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 175

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
Note:
Data register high (ADCDRH)
Reset value: xxxx xxxx (xxh)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
ADC control/data register low (ADCDRL)
Reset value: 0000 00xx (0xh)
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = AMPCAL Amplifier calibration bit
Bit 3 = SLOW Slow mode bit
Table 56.
1. The maximum allowed value of f
Bit 2 = AMPSEL Amplifier selection bit
When AMPSEL=1 it is mandatory that f
Bits 1:0 = D[1:0] LSB of analog converted value
D9
This bit is set and cleared by software. It is advised to use this bit to calibrate the ADC
when amplifier is ON. Setting this bit internally connects amplifier input to 0V. Hence,
corresponding ADC output can be used in software to eliminate amplifier-offset error.
0: Calibration off
1: Calibration on (The input voltage of the amplifier is set to 0V)
This bit is set and cleared by software. It is used together with the SPEED bit in the
ADCCSR register to configure the ADC clock speed as shown on the table below.
This bit is set and cleared by software.
0: Amplifier is not selected
1: Amplifier is selected
7
0
7
Configuring the ADC clock speed
D8
0
D7
0
f
f
f
ADC
ADC
CPU
CPU
f
CPU
is 4 MHz (see
(1)
/2
/4
AMPCAL
D6
ADC
Read/write
Read only
be less than or equal to 2 MHz.
Section 13.11 on page
SLOW
D5
AMPSEL
D4
226)
SLOW
0
0
1
On-chip peripherals
D3
D1
SPEED
0
1
x
D2
175/245
D0
0
0