ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 147

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
11.5.5
11.5.6
6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
10. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
11. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Low power modes
Table 46.
Interrupts
Figure 72. Event flags and interrupt generation
Table 47.
1. The I
Mode
Wait
Halt
Arbitration Lost Event (Multimaster configuration)
subsequent EV4 is not seen.
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is
reset (RIM instruction).
*
EVF can also be set by EV6 or an error from the SR2 register.
10-bit Address Sent Event (Master mode)
Start Bit Generation Event (Master mode)
STOPF
ADD10
BERR
ARLO
ADSL
2
Address Matched Event (Slave mode)
C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
*
BTF
Stop Detection Event (Slave mode)
SB
AF
In Halt mode, the I
I
2
C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Acknowledge Failure Event
Effect of low power modes on the I
Description of interrupt events
End of byte Transfer Event
Interrupt event
Bus Error Event
I
2
2
C interrupts cause the device to exit from Wait mode.
C interface is inactive and does not acknowledge data on the bus. The
(1)
No effect on I
ITE
I
2
Halt mode” capability.
C registers are frozen.
Description
2
2
C interface
C interface.
STOPF
ADD10
BERR
Event
ARLO
ADSL
BTF
flag
SB
AF
control
Enable
ITE
bit
INTERRUPT
EVF
On-chip peripherals
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
from
147/245
Exit
Halt
No
No
No
No
No
No
No
No