ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 165

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
11.6.7
11.6.8
Table 51.
Note:
SPI End of Transfer Event
Master Mode Fault Event
Overrun Error
Interrupt event
Figure 79. Single master / multiple slave configuration
Low power modes
Table 50.
Interrupts
Interrupt events
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Wait
Halt
Mode
5V
Low power mode descriptions
MOSI
SCK
SS
SCK
MOSI
Master
Device
Device
Slave
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the device is
woken up by an interrupt with “exit from Halt mode” capability. The data received
is subsequently read from the SPIDR register when the software is running
(interrupt vector fetching). If several data are received before the wakeup event,
then an overrun error is generated. This error can be detected after the fetch of
the interrupt routine that woke up the Device.
MISO
MISO
SS
MODF
Event
SPIF
OVR
flag
MOSI
SCK
Device
Slave
MISO
Enable control
SS
SPIE
bit
Description
SCK
MOSI
Device
Slave
MISO
Exit from Wait
SS
Yes
On-chip peripherals
MOSI
SCK
Device
Slave
Exit from Halt
MISO
SS
No
No
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