ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 205

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
13.5.2
SPI interface
Subject to general operating conditions for V
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SS, SCK, MOSI, MISO).
Table 82.
1. Data based on design simulation, not tested in production.
2. Depends on f
t
t
t
w(SCKL)
t
w(SCKH)
1/t
t
t
t
Symbol
t
t
dis(SO)
t
t
t
su(SS)
t
su(MI)
t
v(MO)
h(MO)
su(SI)
a(SO)
v(SO)
h(SO)
h(SS)
h(MI)
t
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPI clock rise and fall time
SPI interface characteristics
Data output access time
Data output disable time
SCK high and low time
CPU
Data output valid time
Data output valid time
Data output hold time
Data output hold time
Data input setup time
SPI clock frequency
Data input hold time
SS setup time
. For example, if f
SS hold time
Parameter
(2)
CPU
= 8 MHz, then T
enable edge)
enable edge)
Master (after
f
f
Conditions
Slave (after
CPU
CPU
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
=8 MHz
=8 MHz
DD
, f
CPU
OSC
= 1/f
, and T
CPU
(4 x T
=125 ns and t
A
f
CPU
see I/O port pin description
0.0625
unless otherwise specified.
Min
CPU
120
100
100
100
100
100
90
0
0
0
0
/128
Electrical characteristics
) + 50
su(SS)
= 550 ns
f
f
CPU
CPU
Max
240
120
120
120
2
4
/4
/2
205/245
MHz
Unit
ns