ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 150

IC MCU 8BIT 8K FLASH 32LQFP

ST7FLITE49K2T6TR

Manufacturer Part Number
ST7FLITE49K2T6TR
Description
IC MCU 8BIT 8K FLASH 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITE49K2T6TR

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE49K2T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST7FLITE49K2T6TR
Manufacturer:
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0
On-chip peripherals
150/245
I
Reset value: 0000 0000 (00h)
Bit 7 = EVF Event flag
Bit 6 = ADD10 10-bit addressing in Master mode
Bit 5 = TRA Transmitter/Receiver bit
Bit 4 = BUSY Bus busy bit
2
C status register 1 (I2CSR1)
EVF
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in
hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the peripheral
is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
This bit is set by hardware on detection of a Start condition and cleared by hardware on
detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
7
BTF=1 (byte received or transmitted)
ADSL=1 (Address matched in Slave mode while ACK=1)
SB=1 (Start condition generated in Master mode)
AF=1 (No acknowledge received after byte transmission)
STOPF=1 (Stop condition detected in Slave mode)
ARLO=1 (Arbitration lost in Master mode)
BERR=1 (Bus error, misplaced Start or Stop condition detected)
ADD10=1 (Master has sent header byte)
Address byte successfully transmitted in Master mode.
ADD10
TRA
BUSY
Read Only
BTF
Figure
ADSL
71. It is also cleared by
M/SL
ST7LITE49K2
SB
0

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