ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 143
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ST7FLITE49K2T6
Manufacturer Part Number
ST7FLITE49K2T6
Description
IC MCU 8BIT 8K FLASH 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE49K2T6TR.pdf
(245 pages)
Specifications of ST7FLITE49K2T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITE49K2T6
Manufacturer:
ST
Quantity:
3 000
Company:
Part Number:
ST7FLITE49K2T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST7FLITE49K2T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST7LITE49K2
Note:
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see
EV4).
Error cases
●
●
In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits
transmitted are all 0. It is then necessary to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
ST7 I
SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave
Driver For ST7 I
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
2
C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes,
2
C Peripheral.
Figure 71
Transfer sequencing
On-chip peripherals
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