ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 181
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ST7FLITE49K2T6
Manufacturer Part Number
ST7FLITE49K2T6
Description
IC MCU 8BIT 8K FLASH 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE49K2T6TR.pdf
(245 pages)
Specifications of ST7FLITE49K2T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITE49K2T6
Manufacturer:
ST
Quantity:
3 000
Company:
Part Number:
ST7FLITE49K2T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST7FLITE49K2T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST7LITE49K2
Note:
Comparator control register (CMPxCR)
Reset Value: 1000 0000 (80h)
Bit 7 = CHYST Comparator hysteresis enable
This bit is set or cleared by software and set by hardware reset. When this bit is set, the
comparator hysteresis is enabled.
To avoid spurious toggling of the output of the comparator due to noise on the voltage
reference, it is recommended to enable the hysteresis.
Bit 6 = Reserved, Must be kept cleared
Bit 5 = CINV Comparator output inversion select
This bit is set or cleared by software and cleared by hardware reset. When this bit is set, the
comparator output is inverted.
If interrupt enable bit CMPIE is set in the CMPCR register, the CINV bit is also used to select
which type of level transition on the comparator output will generate the interrupt. When this
bit is reset, interrupt will be generated at the rising edge of the comparator output change
(COMP signal, refer to
generated at the falling edge of comparator output change (COMP signal, refer to
on page
Bit 4 = CMPIF Comparator interrupt flag
This bit is set by hardware when interrupt is generated at the rising edge (CINV = 0) or
falling edge (CINV = 1) of comparator output. This bit is cleared by reading the CMPCR
register. Writing to this bit does not change the value.
Bit 3 : CMPIE Comparator interrupt enable
This bit is set or reset by software and cleared by hardware reset. This bit enables or
disables the interrupt generation depending on interrupt flag
CHYST
0: Hysteresis disabled
1: Hysteresis enabled
0: Comparator output not inverted and interrupt generated at the rising edge of COMP
1: Comparator output inverted and interrupt generated at the falling edge of COMP
0 : Comparator interrupt flag cleared
1 : Comparator interrupt flag set and can generate interrupt if CMPIE is set.
0: Interrupt not generated
1: Interrupt generated if interrupt flag is set
7
179).
0
Figure 82 on page
CINV
CMPIF
Read/write
179). When this bit is set, interrupt will be
CMPIE
CMP
On-chip peripherals
COUT
Figure 82
CMPON
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