ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 230

IC MCU 8BIT 8K FLASH 32LQFP

ST7FLITE49K2T6

Manufacturer Part Number
ST7FLITE49K2T6
Description
IC MCU 8BIT 8K FLASH 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITE49K2T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ST
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STMicroelectronics
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Device configuration and ordering information
14
14.1
14.1.1
230/245
Device configuration and ordering information
This device is available for production in user programmable version (Flash).
ST7LITE49K2 XFlash devices are shipped to customers with a default program memory
content (FFh).
Option bytes
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
Option byte 1
Bits 7:6 = CKSEL[1:0] Start-up clock selection.
Table 106. Startup clock selection
Bit 5 = Reserved, must always be 1.
Bit 4 = PLL32OFF 32 MHz PLL disabled.
Bits 3:2 = LVD[1:0] Low voltage detection selection.
Table 107. LVD threshold configuration
These bits are used to select the startup frequency. By default, the internal RC is
selected.
0: PLL32 enabled
1: PLL32 disabled (by-passed). By default the PLL32 is disabled.
These option bits enable the low voltage detection block (LVD) with a selected
threshold as shown in
External crystal/ceramic resonator
Internal RC as startup clock
AWU RC as a startup clock
Configuration
External clock
Medium voltage threshold
Highest voltage threshold
Lowest voltage threshold
LVD Off (default value)
Table
Configuration
107.
CKSEL1
0
0
1
1
VD1
1
1
0
0
ST7LITE49K2
CKSEL0
0
1
0
1
VD0
1
0
1
0

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