ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 60

• Manufacturer Part Number: ST7FLITE49K2T6
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupts
Caution:
60/245
The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is
kept (Example: previous = CFh, write = 64h, result = 44h).
Table 16.
1. Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 17.
1. During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the
Instruction
POP CC
management.
current software priority up to the next IRET instruction or one of the previously mentioned instructions.
JRNM
TRAP
HALT
IRET
JRM
RIM
WFI
SIM
Interrupt vector vs ISPRx bits
Dedicated interrupt instruction set
Disable interrupt (level 3 set)
Enable interrupt (level 0 set)
Jump if I1:0 = 11 (level 3)
Vector address
Pop CC from the Stack
Interrupt routine return
FFFBh-FFFAh
FFE1h-FFE0h
FFF9h-FFF8h
Entering Halt mode
Jump if I1:0 <> 11
New description
Wait for interrupt
Software trap
...
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Function/Example
Pop CC, A, X, PC
Software NMI
Mem => CC
I1:0 <> 11
I1:0 = 11
(1)
I1_13 and I0_13 bits
I1_0 and I0_0 bits
I1_1 and I0_1 bits
ISPRx bits
I1
I1
I1
1
1
1
1
1
...
H
H
H
I0
I0
I0
0
0
1
1
0
(1)
ST7LITE49K2
N
N
N
Z
Z
Z
C
C
C