ST7FLITE49K2T6 STMicroelectronics, ST7FLITE49K2T6 Datasheet - Page 99

• Manufacturer Part Number: ST7FLITE49K2T6
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
Bits 4:3 = CK[1:0] Counter clock selection bits
Table 37.
Bit 2 = OVF1 Overflow flag
Bit 1 = OVFIE1 Overflow Interrupt Enable bit
Bit 0 = CMPIE Compare Interrupt Enable bit
Counter register 1 high (CNTR1H)
Reset value: 0000 0000 (00h)
Counter register 1 low (CNTR1L)
Reset value: 0000 0000 (00h)
Bits 15:12 = Reserved
CNTR1_7
These bits are set and cleared by software and cleared by hardware after a reset. they
select the clock frequency of the counter.
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value.
0: No Counter Overflow Occurred
1: Counter Overflow Occurred
This bit is read/write by software and cleared by hardware after a reset.
0: Overflow Interrupt Disabled.
1: Overflow Interrupt Enabled.
This bit is read/write by software and cleared by hardware after a reset. it can be used
to mask the interrupt generated when any of the cmpfx bit is set.
0: Output Compare Interrupt Disabled.
1: Output Compare Interrupt Enabled.
15
7
0
CNTR1_6
Counter clock selection
0
f
LTIMER
Counter clock selection
CNTR1_5
(1 ms timebase @ 8 MHz)
0
32 MHz
OFF
f
CPU
CNTR1_4
0
Read only
Read only
CNTR1_3
CNTR1_
11
CNTR1_2
CNTR1_
10
CNTR1_9
CNTR1_1
On-chip peripherals
CK1
0
1
0
1
CNTR1_8
CNTR1_0
CK0
0
1
1
0
8
0
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