ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 125

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
11.4.7
Note:
11.4.8
Note:
Interrupts
Table 53.
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Register description
SPI control register (SPICR)
Reset value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable
Bit 6 = SPE Serial Peripheral Output Enable
Bit 5 = SPR2 Divider Enable
This bit has no effect in slave mode.
7
SPI end of transfer event
Master mode fault event
Overrun error
SPIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault
or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see
reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
Interrupt event
Interrupt events
SPE
Master mode fault (MODF) on page
SPR2
Event flag
Doc ID 12321 Rev 5
MODF
SPIF
OVR
MSTR
Read/Write
Enable control
Table 54: SPI master mode SCK
SPIE
CPOL
bit
CPHA
121). The SPE bit is cleared by
Exit from Wait
Yes
On-chip peripherals
SPR1
Exit from Halt
0
frequency.
Yes
No
SPR0
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