ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 84

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

On-chip peripherals
Note:
11.1.4
11.1.5
Caution:
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The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
●
Using Halt mode with the WDG
If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
How to program the watchdog timeout
Figure 38
counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a
quick calculation without taking the timing variations into account. If more precision is
needed, use the formulae in
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 38. Approximate timeout duration
Watchdog reset on Halt option
If the watchdog is activated and the watchdog reset on halt option is selected, then the
HALT instruction will generate a Reset.
3F
38
30
28
20
18
10
08
00
1.5
shows the linear relationship between the 6-bit value to be loaded in the watchdog
18
34
Watchdog timeout (ms) @ 8 MHz f
Figure
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39.
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OSC2
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ST72344xx ST72345xx
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