ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 90

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

On-chip peripherals
11.2.7
Note:
90/247
Register description
MCC control/status register (MCCSR)
Reset value: 0000 0000 (00h)
Bit 7 = MCO Main clock out selection
To reduce power consumption, the MCO function is not active in Active-halt mode.
Bits 6:5 = CP[1:0] CPU clock prescaler
Table 41.
Bit 4 = SMS Slow mode select
Bits 3:2 = TB[1:0] Time base control
These bits select the programmable divider time base. They are set and cleared by
software.
MCO
This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by
software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (f
These bits select the CPU clock prescaler which is applied in the different slow modes.
Their action is conditioned by the setting of the SMS bit. These two bits are set and
cleared by software.
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See
page 82
7
Section 9.2: Slow mode
CPU clock prescaler selection
for more details.
CP1
f
CPU
CPU
f
in Slow mode
f
f
f
OSC2
OSC2
OSC2
OSC2
CPU
is given by CP1, CP0
CP0
/ 16
=
/ 2
/ 4
/ 8
f
OSC2
Doc ID 12321 Rev 5
and
SMS
Section 11.1: Window watchdog (WWDG) on
Read/Write
CPU
on I/O port)
TB1
CP1
TB0
0
0
1
1
ST72344xx ST72345xx
OIE
CP0
0
1
0
1
OIF
0